1. Field of the Invention
The present invention relates in general to a method for forming contact holes, and more particularly, to a method for forming contact holes for a memory device.
2. Description of the Related Art
As semiconductor device geometries continue to decrease in size to provide more devices per fabricated wafer and faster devices, misalignment between each patterned layer is a serious obstacle. Therefore, many self-aligned processes have been developed in order to prevent misalignment and decrease the interval between devices, thereby increasing the device density.
FIGS. 1a to 1d are cross-sections showing a conventional method of forming contact holes for a memory device. First, in FIG. 1a, a silicon substrate 100 is provided. The substrate 100 may contain any semiconductor device, such as MOS transistors and capacitors, used in the memory devices. Here, in order to simplify the diagram, only a flat substrate is depicted. Moreover, the substrate 100 has a memory array region 10 and a peripheral circuit region 20.
Next, a plurality of gate structures 109 is formed overlying the memory array region 10 and the peripheral circuit region 20, wherein the gate structure 109 comprises a gate dielectric layer (not shown), a gate 104, a gate capping layer 106, and a gate spacer 108. The gate dielectric layer may be a silicon oxide layer formed by thermal oxidation. The gate 104 may comprise polysilicon. The gate capping layer 106 and the gate spacer 108 may comprise silicon nitride.
Thereafter, an insulating layer 110, such as a borophosphosilicate glass (BPSG) layer, is formed on the gate structures 109 and fills the gaps therebetween to serve as an interlayer dielectric (ILD) layer. Next, a photoresist layer 114 is coated on the insulating layer 110 and lithography is performed to form openings 117, 119, and 121 therein to expose the insulating layer 110.
Next, in FIG. 1b, the insulating layer 110 under the openings 117, 119, and 121 is etched using the photoresist layer 114 as an etch mask and using the gate capping layers 106, the gate spacers 108, and the substrate 100 as stop layers to simultaneously form bit line contact holes (CB) 123 on the memory array region 10 to expose the substrate 100 and the gate spacers 108 and form substrate contact holes (CS) 127 and gate contact holes (CG) 125 on the peripheral circuit region 20 to expose the substrate 100 and the gate capping layers 106, respectively.
Next, in FIG. 1c, after the photoresist layer 114 is removed, a photoresist layer 128 is coated on the insulating layer 110 and fills the bit line contact holes 123, the substrate contact holes 127, and the gate contact holes 125. Next, lithography is performed to remove the photoresist layer 128 in the gate contact holes 125.
Finally, in FIG. 1d, the gate capping layers 106 under the gate contact holes 125 are etched using the remaining photoresist later 128 as an etch mask to expose the gate 104, thereby completing the fabrication of the gate contact holes 125. Thereafter, the remaining photoresist layer 128 is removed.
However, in this method, in order to prevent damaging the gate capping layer 106 and the gate spacer 108 under the bit line contact hole 123 during etching the gate capping layer 106 under the gate contact hole 125, an additional masking layer 128 must be formed by lithography. As a result, the fabrication of contact holes is complicated, increasing fabricating cost. Moreover, misalignment may occur easily when the additional masking layer is formed, reducing device yield.